Intel TLM implementation (Aztalan)

The contribution from Intel is an intermediate abstraction level TLM framework for SystemC. It provides a set of initiator and target ports, application-specific protocol interfaces (isc_tlm_master_if, isc_tlm_slave_if, isc_tlm_master_slave_if), an isc_tlm_channel class, an isc_tlm_transport class, an isc_tlm_pipeline_t class and a variety of associated subclasses. The framework enables the creation of systems which are very close to or even at (this depends on the system’s complexity) a BA level of abstraction.

A system must comprise of at least one master, one slave and an isc_tlm_channel instance (including all required subinstances). The master has to posess an isc_master_port that is connected to the channel via a port-to-channel binding, while the slave has to posess an isc_slave_port that is connected to the same channel in the same way. The channel has to be configured with a valid protocol specification (e.g. AXI), which can be read from an XML file.

Transactions always begin with a master creating and configuring an isc_request instance and afterwards sending the request to the channel via the send API method. The request contains all transaction related information, like timing mode of the master, target address, request type (read or write) tranferred data, user tags and, in case implicit timing is used, delay information. The following description of a data transfer relates to explicit timing. After the send call the channel starts simulating the busses request/grant behaviour, signalling the grant of the bus to the master with an event. Triggered by this event, the master will call send_address whereupon the channel simulates the bus’s addressing behaviour using the delays from the bus-protocol and the delays provided as arguments of the calling method and subsequently informs the targeted slave with an event that it is beeing addressed. Receiving this event, the slave fetches the active addressed_phase of his isc_slave_port, stores all required information in this phase object (like its timing mode and the acknowledge mode) and acknowledges the address by calling the send_address_ack method including the request ID and the acknowledge delay. This acknowledge passes the channel beeing delayed according to the bus’s protocoll and to the given delay value and then triggers the address_ack_event in the master port. Depending on the request type either the master (in case of a write) or the slave (in case of a read) will receive an data_ack_event, after which data has to be put onto the channel by calling write_data. The data to be written is put into the requests data buffer. The delaying mechanism equals the one used for delaying the address information. After the delay the channel signalizes the availability of data to the data receiver by triggering the data_ready_event. Then the data receiver calls the read_data method and the data is read from the bus. Noting that the data has been read, the channel informs both master and slave with the complete_event, that the transaction is finished.

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