This is a discussion group.

While the upcoming TLM-2 standard provides mechanisms for modeling bus transactions, it does not address the need to model bus-visible registers and memories.

One way of looking at ths is the Software interface to the silicon based functionality. This opens the possibility that the functionality may be implemented partially in hardware, and partially in software, so long as the software interface is provided.

A different aspect of this is that it could assist and easy modeling, a structured mechanism for building these registers, memories, and address decode is needed. In addition, this mechanism needs to support an easy path to implementation using high-level synthesis without rewriting the code.