PciExpress

PCI Express Bus Model

This project provides a PCI Express bus model for GreenBus. It may be used at the abstration level PV (Programmer's View) or AV (Architect's View).

Call for Use Cases

Specifications and Tasks

Implementation

For the code download please use the release mechanism.


Thoughts on timing


Documentation:

  • Specifications and Tasks

    • Level of abststraction: PV (Programmer's View)
    • Extensible to model PCI-like buses (e.g. subset of PCIe).
    • Transaction container
  • Timing aspects of the PCIe protocol

    We do PV communication with blocking calls and no timing simulation.

    If we add timing later these thoughts may be helpful:

    Phases

    Phases:
  • Use Cases

    Please add Use Cases!!

    Demonstration platform

    <code>

           TG
            |
     PCIe root complex
            |
         PCIe router
         |         |
    PCIe Bridge Mem /2nd router
      |      |
    PCIe PCIe Dev.2 Dev.1

  • PCI Express Implementation

license: 
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