Timing aspects of the PCIe protocol

We do PV communication with blocking calls and no timing simulation.

If we add timing later these thoughts may be helpful:

Phases

Phases:

• Request,
• RequestCompletionError,
• RequestCompletion

Communication flow FlowControl

Data Link Layer Packets (DLLPs) for Flow Control, field DLLP_Type: (see p.144,112,138, sec.3.3.1)
Using phase 'Request'.

• InitFlowControlPostedRequest, InitFlowControlNonPostedRequest, InitFlowControlCompletion,
• InitFlowControl2PostedRequest, InitFlowControl2NonPostedRequest, InitFlowControl2Completion,
• UpdateFlowControlPostedRequest, UpdateFlowControlNonPostedRequest, UpdateFlowControlCompletion

Phases and Transactions

The types MRd, IORd, CfgRd0, CfgRd1, IOWr, CfgWr0, CfgWr1, MRdLk use three phases for transacting their packets. Typically a communication flow consists of the two phases Request and Completion which represent two PCIe packets. The communication flow of the read types (MRd, IORd(?), MRdLk) may consist of more than one Completion if the read data does not fit into one packet. For these cases we have the following problem:

Originally in PCIe these Completions are separate packets which are sent independently by the slave. The correct transmitting order is guarantied but these Completion packets may be on the line at the same time. If we model these transaction flow with only one transaction where each original packet is modeled with one atom we are not able to model the concurrency of two Completion packets. We have to keep this in mind, but it does not represent a problem since we do PV and have no timing.

ImageLink(RequestCompletionProblem.jpg)