Simics™ SystemC Bridge

SystemC Simulation Kernel in Simics™ Environment

This is currently a placeholder, please considering registering yourself for this group to keep in touch with developments, and get in touch with Virtutech for more information.

The technique is applicable to many SystemC integrations with other simulation kernels which have some notion of time, and events. It is possible because of the OSCI TLM 2.0 notion of "time warping" which is embodied in the TLM 2.0 (draft) standard.

active?fid=37

The goals of this project are to :

  • Provide access to the SystemC kernel in Simics
    • Device communications interfaces
  • Memory map
    • Incoming reads and writes from processor and others
  • To other devices
    • Interrupts, reset lines, ... within a chip
  • Back-end input/output
    • Networks, serial lines, buses, ...
    • SystemC kernel interface to devices
  • Provide this Automatic given that the kernel runs in Simics

Documentation:

 None.
No Releases
issues: 
All
Bugs
submit bug
Support Requests
submit support request
Features Requests
submit feature request
Mail List: 
This group has no email list, all issues will only be posted on the web interface
SVN Repository: 

Posted March 6th, 2008 by JaakkoVarteva