ComparisonOfHDLs
Comparison of HDLs
There are several tasks that need to be fulfilled during the design process, e.g. system modeling and architecture design, development of algorithms, (functional) verification, etc...
Several languages and methodologies have been developed for this purpose, whereas no language can provide an ultimate solution.
The following table provides a comparison of different languages that are being used in EDA-style design. The amount of {OK} will indicate the fitness for purpose of particular tasks.
| SystemC | VHDL/Verilog | System-Verilog | UML, SDL | Matlab, C++ | Vera, e, PSL/Sugar | |
| colspan=7 | | ||||||
| System modeling | <:> {OK} {OK} | <:> --- | <:> --- | <:> {OK} {OK} {OK} | <:> --- | <:> --- |
| Software / Algorithms | <:> {OK} {OK} | <:> --- | <:> --- | <:> --- | <:> {OK} {OK} {OK} | <:> --- |
| Transaction Level | <:> {OK} {OK} {OK} | <:> --- | <:> {OK} | <:> --- | <:> --- | <:> --- |
| Behavioral | <:> {OK} {OK} | <:> {OK} {OK} | <:> {OK} {OK} | <:> --- | <:> --- | <:> --- |
| RTL | <:> {OK} | <:> {OK} {OK} {OK} | <:> {OK} {OK} {OK} | <:> --- | <:> --- | <:> --- |
| Verification | <:> {OK} | <:> (./) | <:> {OK} {OK} | <:> --- | <:> --- | <:> {OK} {OK} {OK} |
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Posted January 8th, 2008 by MarkBurton