GreenReg

Model Construction
GreenReg provides a Device and Register framework to assist in the construction of Device IP blocks. It greatly simplifies the description of registers, state machines for running the bus interface.

The original work was made available by Intel. It was the original brain-child of Jason Patrick.

GreenReg provides a very simple SystemC syntax for defining registers, and how they connect to state machines. The decoding, storage and callbacks are then all dealt within by the GreenReg framework, meaning that the user simply defines the registers and the functionality, and does not need to worry about the bus interaction, register memories, or access decoding.

A wide variety of (complex) register structures are supported.

Key Aspects of GreenReg:

  • Intended for rapid development and maintainability of ESL models.
  • TLM bus independence with simplified transactions.
Construction
Downloads: 
Part of core infrastructure.
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