Regression Tests

Regression tests are performed within the PCIe example examples/PCIe/platform.

This is the test platform:

These are the tests that have already been done.

• Memory Address Map
  • Check for overlapping address ranges: Checked overlapping address ranges of devices connected to different routers. Check finds error in the upstream router. (See example/PCIe/platform.) This test also applies for the identical I/O Address map.
• Routing tests (see example/PCIe/platform):
  • Memory and I/O Address Maps
    • Check for correct routing: Use define ENABLE_ROUTING_TEST_SCENARIO in platform_globals.h. This replaces device 'send1' with a routing test device which sends Memory and I/O transactions to different receivers. All TLPs are received at the correct receiver device (see svn rev. 2433). The addresses are set according the image above.
  • ID based routing:
    • Configuration Requests routed from the Root Complex to each existing device due to propagation of Bus and Device Numbers see Interrupt Scenario (use define ENABLE_INTERRUPT_SCENARIO).
  • Implicit Routing:
    • Broadcast: see Power Management PME_Turn_Off Message
    • Gathered and routed to root complex: see Power Management PME_TO_Ack Message
• Lock / Unlock (in VC0)
  • See example/PCIe/platform and topology image example_pcie_platform_topology.odg with locked path (svn rev. 2411). Use define ENABLE_LOCKED_TEST_SCENARIO to enable this test scenario (file platform_globals.h).
  • Sending Memory Read Locked from Root Complex to recv4 device: results in a locked path which cannot be used by other devices.
  • Other communication which does not use the locked path works furthermore.
  • After sending the Unlock Message normal communication works again.
  • The Root Complex has to use Locked Memory Read TLPs instead of Memory Read TLPs when locked (error if not using locked ones, check with define ENABLE_NEG_LOCKED_TEST_SCENARIO).
  • The Root Complex may send Memory Writes to the locked device.
  • The Root Complex may only send to the locked device.
  • Unlock Message unlocks the path.

• Power Management PME_Turn_Off and Ack
  • See example/PCIe/platform and topology image example_pcie_platform_topology.odg (svn revision 2419). Use define ENABLE_PME_SCENARIO to enable this test scenario (file platform_globals.h).
  • Send PME_Turn_Off is broadcasted to all devices.
  • Alle devices react with a PME_TO_Ack message.
  • The PME_TO_Ack routing to Root Complex is done correctly.
  • The Root Complex can turn off power after received PME_TO_Ack.
• Integration of Generic Devices to PCIe (Testplatform: example/PCIe/generic, example/PCIe/mixed)
  • Communication between only Generic Devices with replaced headers (see example/PCIe/generic, define USE_PCIE_GENERIC and USE_GENERIC_ROUTER_CONNECT in example_generic_pcie.cpp).
  • Communication PCIe Sender (Master) to Generic Slave (see example/PCIe/mixed - part 1).
    • Generic Error injected by Generic Slave results in Error Completion Status at PCIe Sender (done with example/PCIe/mixed injected simplebusApi.h).
    • PCIe Sender sends an unknown transaction type (not MemoryRead/MemoryWrite) to a Generic Slave: results in warning message at Slave (see example/PCIe/mixed) and in a completion status error.
  • Communication Generic Sender (Master) to PCIe Receiver (see example/PCIe/mixed - part 2).
    • PCIe Completion Error injected by PCIe Receiver results in Error at Generic Master (see example/PCIe/mixed - PCIeRecvDevice2.cpp).
    • Generic Master send a not supported transaction type to a PCIe Receiver: results in 'Unsupported TLP type' warning.
• Integration of PCIe Devices to Generic Router (Testplatform: example/PCIe/generic)
  • Communication between PCIe Device (Sender) and Generic (Slave) Devices (without wrapper). (see example/PCIe/generic, define USE_PCIE_GENERIC and USE_GENERIC_ROUTER_CONNECT in example_generic_pcie.cpp). Successful Memory Read including the setting of the completion status.
  • Communication between PCIe Device (Sender and Receiver) and Generic (Slave) Devices and Master Devices (itself) with the Wrapper PCIe2GenericPortWrapper. The PCIe Device successfully performs a Memory Read with successful Completion. The PCIe Device successfully sends a Memory Write to itself (routed through the Generic Router).