SystemC/LanguageOverview

The language overview describes the architecture of the SystemC library which utilizes a layered approach built on ANSI C++. When using a layered approach (as shown in the table), it becomes possible to add specific libraries or higher-level constructs to a system-level design. Prominent examples are the SystemC Verification Library (SCV) or generic busses, like the GreenBus.

The core of the SystemC library consists of an efficient simulation engine for HW/SW Co-Design. The library provides ways to model hierarchical entities at different levels of abstraction. Moreover communication can be described in a flexible way, thus Transaction Level Modeling becomes more interesting.

<:> SystemC Verification Library, Master/Slave Library, Application specific libraries

<:style="background-color: #E0E0FF;"> Elementary Channels

<:style="background-color: #E0E0FF;"> Core Language, SystemC Data Types

<:> ANSI C++

To extend SystemC and its capabilities powerful components are needed, which in turn can easily be added to a existing design. This enables complex systems consisting of multiple hardware and software components.

The Core Language

Almost all language constructs of SystemC are prefixed with SC_ or sc_.

 Modules:: are the basic building blocks of each design. A module can be seen as an entity in VHDL, or as a class in C++ (in fact it is, so it can inherit other modules (classes) and must define a constructor, e.g. 5).

 Ports:: allow modules to communicate with each other. There exist general purpose 6, 7 and 8 ports. Moreover, a 9 can use a dedicated interface, to implement higher-level communication techiques.

 Processes:: implement the behaviour of a module and are declared as member functions inside the module. There are three different types of processes, for example 10s. A more detailed description is here.

 Interfaces:: facilitate a separation of interface and implementation, i.e. they generally define virtual 11 and 12 functions that manipulate a channel. Interfaces can be seen as the 'signature' of channels.

 Channels:: are bound to ports, i.e. any data between several modules is transferred through channels. Hence, a port of a module can use access methods defined in interfaces and declared/implemented in channels.

 Events:: are the basic synchronization elements of the SystemC language. Events can be notified in order to trigger the execution of processes.

Information on SystemC Data Types and C++ Data Types

SystemC supports data types for appropriate hardware modeling. Available are 4-valued logic types and 4-valued logic vectors (0,1,X,Z). Furthermore there are types for single bits and bit-vectors, as well a precision integers and fixed-point numbers. One advantage of SystemC is the integration of C++ native types and C++ user-defined types, i.e. you can easily declare structures that hold multiple variables belonging to a specific type. When mixing SystemC and C++ data types, think of converting properly.

Elementary Channels

Elementary Channels are predefined channels to ease basic modeling techniques.

• Signals offer hardware like channels for arbitrary data types. You can think of it as a piece of wire. An event will be generated if and only if the value changes.
• Buffers behave exactly like signals, but an event is generated on every write. Thus, it may be useful when modeling event driven systems.
• FIFOs implement a data queue inside the channel, i.e. the first data item written to the FIFO is the first data item read from the FIFO.
• Mutex implements a mutual exclusion lock, so that only one process may lock a mutex at a given time instance.
• Semaphores implement an extension to mutex, i.e. they apply a resource counter.

---

PageComment2(commentfirst=1,nosmiley=1,articleview=1)

---

NewPage(PublicTemplate,New Page Here,SystemC/LanguageOverview)